1. Field of the Invention
The present invention relates to a manufacturing method of a semiconductor device having a multi-layer wiring structure and, more specifically, to a method of forming contact holes through an interlayer insulating film.
2. Description of the Related Art
In a semiconductor device having a multi-layer wiring structure, upper-layer wiring lines (interconnections) and lower-layer wiring lines are connected to each other such that contact holes are formed through an interlayer insulating film that is formed on the lower-layer wiring lines and the upper-layer wiring lines are formed through the contact holes.
Conventionally, contact holes are required to be tapered to improve the step coverage of upper-layer wiring lines at contact holes. Japanese Unexamined Patent Publication No. 50-123274 discloses a method of tapering a contact hole by forming an interlayer insulating film as two-layer silicon films that are respectively formed through thermal oxidation and CVD and utilizing an etching rate difference between the two layers due to the different methods of forming those layers.
When part of an interlayer insulating film is formed through thermal oxidation as in the conventional example, heating is performed at a temperature of 500xc2x0 C. or more. However, in semiconductor devices such as a thin-film transistor, a wiring line under an interlayer insulating film, that is, a gate electrode is made of aluminum, which tends to diffuse into the surrounding portions when heated at a temperature of 450xc2x0 C. or more. If diffused aluminum passes through a gate insulating film under the gate electrode and further goes into a semiconductor layer under the gate insulating film, there may occur a failure in operation or short-circuiting. For this reason, in a semiconductor device in which a lower-layer wiring line is formed with aluminum, thermal oxidation cannot be employed. Therefore, an interlayer insulating film is formed in a single-layer structure only through CVD method.
To form a tapered contact hole through an interlayer insulating film of a single-layer structure, etching conditions such as an etching time need to be controlled strictly. For example, the etching time is too long, the side wall of a contact hole becomes vertical to the bottom surface, that is, the contact hole cannot be tapered, possibly resulting in disconnection of a wiring line.
Further, to etch an interlayer insulating film completely, overetching of several tens of seconds is generally performed. This may cause a problem that a wedge-shaped recess is formed between a semiconductor layer of a source/drain region and the interlayer insulating film.
Referring to FIG. 4A, reference numeral 401 denotes a crystalline silicon semiconductor layer and numeral 402 denotes an interlayer insulating film that is a single-layer oxide film. In forming a contact hole by etching a desired portion of the interlayer insulating film 402, if there exists a protrusion of dust or the like between the semiconductor layer 401 and the interlayer insulating film 402, an etching liquid may soak through it, resulting in the formation of a wedge-shaped recess 403. As an example of the dust, an oxide or fluoride of aluminum which constitutes an aluminum wiring has been recognized by the inventors of the present invention.
In this case, when a wiring electrode 404 is formed as shown in FIG. 4B, it is difficult to cover the wedge-shaped recess 403, possibly resulting in disconnection of the wiring line. FIGS. 9A and 9B are SEM photographs showing the structure of FIG. 4. FIG. 9B is an enlarged view of an encircled portion of FIG. 9A. In FIG. 9B, reference numerals 404a and 404b are a titanium wiring and an aluminum wiring, respectively.
Where a pixel area or a peripheral driver circuit of an active matrix liquid crystal display device is formed by using thin-film transistors, several hundred to several thousand thin-film transistors are formed on the same substrate at the same time. Since disconnection of a wiring line even in a single thin-film transistor may lead to a failure of the entire substrate, the production yield will be reduced.
An object of the present invention is to provide, by solving the above problems, a manufacturing method of a semiconductor device which method can form, by a common etching method, a tapered contact hole through an interlayer insulating film formed only by CVD.
Another object of the invention is to improve the production yield of semiconductor devices by forming contact holes that are free of recesses and enable good coverage of wiring lines.
To solve the above problems, according to a first aspect of the invention, there is provided a manufacturing method of a semiconductor device, comprising the steps of:
forming a metal conductive layer or a semiconductor layer;
forming an insulating film by CVD so that it covers the metal conductive layer or the semiconductor layer, and that an etching rate of the insulating film increases continuously or in a step-like manner as a position goes up by varying film forming conditions continuously or in a step-like manner; and
forming a contact hole by etching a desired portion of the insulating film.
According to a second aspect of the invention, there is provided a manufacturing method of a semiconductor device, comprising the steps of:
forming a metal conductive layer or a semiconductor layer;
forming an insulating film by CVD so that it covers the metal conductive layer or the semiconductor layer, and that an etching rate of the insulating film increases continuously or in a step-like manner as a position goes up; and
forming a contact hole by etching a desired portion of the insulating film.
According to a third aspect of the invention, there is provided a manufacturing method of a semiconductor device, comprising the steps of:
forming an active layer on a substrate surface;
forming a first insulating film on the active layer;
forming a wiring layer on the first insulating film;
exposing a desired surface portion of the active layer by etching the first insulating film;
forming a second insulating film by CVD so that it covers the exposed surface portion of the active layer and the wiring layer, and that an etching rate of the second insulating film increases continuously or in a step-like manner as a position goes up; and
forming a contact hole by etching a desired portion of the second insulating film.
According to a fourth aspect of the invention, there is provided a manufacturing method of a semiconductor device, comprising the steps of:
forming a wiring layer with aluminum or metal mainly made of aluminum;
forming an insulating film by CVD so that it covers the wiring layer, and that an etching rate of the insulating film increases continuously or in a step-like manner as a position goes up; and
forming a contact hole by etching a desired portion of the insulating film.
According to a fifth aspect of the invention, there is provided a manufacturing method of a semiconductor device, comprising the steps of:
forming a metal conductive layer or a semiconductor layer;
forming an insulating film by CVD so that it covers the metal conductive layer or the semiconductor layer, a lowermost layer of the insulating film being a silicon nitride film of 200 to 500 xc3x85 in thickness; and
forming a contact hole by etching a desired portion of the insulating film.
The silicon nitride film may be formed through plasma CVD by using silane (SiH4), ammonia (NH3), and nitrogen (N2) as material gases. It is desired that the silicon nitride film be so dense as to be etched by buffered hydrofluoric acid at a rate of 800 to 1,000 xc3x85/min.
In the manufacturing method of a semiconductor device according to the first aspect of the invention, in forming an insulating film by CVD so that it covers the metal conductive layer or the semiconductor layer, the film forming conditions are varied continuously or in a step-like manner so that the etching rate of the insulating film increases continuously or in a step-like manner as the position goes up. When this insulating film is etched, the opening becomes smaller as the position goes down, that is, a tapered contact hole is formed.
In the manufacturing method of a semiconductor device according to the second aspect of the invention, an insulating film covering the metal conductive layer or the semiconductor layer is formed by CVD so that the etching rate of the insulating film increases continuously or in a step-like manner as the position goes up. When this insulating film is etched, the opening becomes smaller as the position goes down, that is, a tapered contact hole is formed.
In the manufacturing method of a semiconductor device according to the third aspect of the invention, by exposing a desired surface portion of the active layer by etching the first insulating film under the wiring layer, the active layer and the wiring layer are covered only with a second insulating film that is formed by CVD so that its etching rate increases continuously or in a step-like manner as the position goes up. Thus, tapered contact holes for the active layer and the wiring layer are formed by the same etching step. For example, in manufacturing a thin-film transistor, contact holes for the source/drain regions and the gate electrode are so formed as to assume a tapered profile.
In the manufacturing method of a semiconductor device according to the fourth aspect of the invention, a wiring layer is formed with aluminum or metal mainly made of aluminum, and an insulating film to cover the wiring layer is formed by CVD so that its etching rate increases continuously or in a step-like manner as the position goes up. When this insulating film is etched, the opening becomes smaller as the position goes down, that is, a tapered contact hole is formed through the insulating film. By virtue of the use of CVD, a multi-layer insulating film is formed at such a temperature that there occurs neither diffusion of aluminum that constitutes a wiring line nor abnormal crystal growth of aluminum.
In the manufacturing method of a semiconductor device according to the fifth aspect of the invention, a silicon nitride film of 200 to 500 xc3x85 in thickness is formed as the lowermost layer of an interlayer insulating film. Since the silicon nitride film has a lower etching rate than a silicon oxide film, it not only contributes to formation of a tapered contact hole but also prevents formation of a wedge-shaped recess in a bottom portion of a contact hole.
In the invention, as described above, the film forming conditions are varied continuously or in a step-like manner so as to form insulating films having different etching rates. For example, a silicon nitride film is deposited by plasma CVD as a lowermost layer, and silicon oxide films are deposited by plasma CVD while the rf output value is varied continuously or in a step-like manner. In another example, without depositing a lowermost silicon nitride film, only silicon oxide films are deposited by plasma CVD while the rf output value is varied continuously or in a step-like manner.
That is, to form insulating films having multiple layer of different etching rates, it is utilized that films having different compositions such as a silicon nitride film and a silicon oxide film exhibit different etching rates, and that the etching rate of a silicon oxide film is higher when the rf output value is smaller.